Ashwini Vaishnaw Signals Scale-Up of India’s Fabless Chip Push Under DLI Scheme

To support this, the government has provided advanced EDA tools, resulting in nearly 2.25 crore tool-hours of usage, with 67,000 students and over 1,000 startup engineers actively engaged.

India’s ambition to become a global semiconductor design powerhouse received fresh momentum as Union Minister for Electronics and Information Technology Shri Ashwini Vaishnaw today interacted with chip design companies supported under the Design Linked Incentive (DLI) Scheme of the Semicon India Programme in New Delhi.

The interaction focused on reviewing progress across India’s fast-growing fabless ecosystem, showcasing indigenous chip innovations, and reinforcing the government’s long-term commitment to building a self-reliant semiconductor design base spanning startups, academia and industry.

From modest beginnings to real silicon

Launched in 2022, the DLI Scheme was initially seen as an experimental push. Four years on, it now supports 24 semiconductor startups, many of which have already completed tape-outs, validated products, and secured early market traction—a milestone rarely achieved so quickly in deep-tech ecosystems.

“These outcomes validate our ecosystem-driven approach,” the Minister said, noting that India’s semiconductor strategy was designed as a multi-year national mission, not a collection of isolated incentives. The goal, articulated by Prime Minister Narendra Modi, is to transform India from a services-led economy into a product nation.

What India’s chip designers are building

DLI-backed companies are designing chips across a wide technology spectrum, including:

• Indigenous SoCs and ASICs for surveillance, networking and embedded systems

• RISC-V–based processors and accelerators

• AI-enabled, low-power chips for IoT and edge applications

• Telecom and wireless chipsets

• Power management and mixed-signal ICs

• Chips for automotive, energy, space and defence

To support this, the government has provided advanced EDA tools, resulting in nearly 2.25 crore tool-hours of usage, with 67,000 students and over 1,000 startup engineers actively engaged.

Tape-outs, patents and funding traction

The design push is translating into tangible outputs:

• 122 academic designs taped out, with 56 chips fabricated at 180 nm at SCL, Mohali

• 16 startup tape-outs, resulting in six chips fabricated at advanced nodes as small as 12 nm

• 85 patents filed (75 by academia, 10 by startups)

• ₹430 crore in venture capital funding attracted, with 14 of 24 startups securing VC backing

For global observers, this signals a maturing ecosystem moving beyond prototypes to real silicon and capital confidence.

Scaling up: 50 fabless companies next

Calling India Semiconductor Mission’s support architecture “globally unique,” Shri Vaishnaw said the government now plans to scale the DLI Scheme to at least 50 fabless semiconductor companies in its next phase. The support model—combining access to design tools, IP libraries, wafer supply and tape-out funding—has helped remove the biggest entry barriers for chip startups.

He expressed confidence that India will soon see globally competitive fabless firms comparable to leading international players.

Infrastructure, talent and global perception shift

On the manufacturing side, SCL Mohali will continue supporting 180 nm tape-outs, while advanced nodes up to 28 nm will be enabled through the upcoming Dholera fab, creating a stronger design–manufacturing bridge.

Talent development has also outpaced targets. Against a 10-year goal of 85,000 skilled professionals, over 67,000 semiconductor professionals have already been trained in just four years across 315 academic institutions.

Sharing feedback from recent global engagements, including the World Economic Forum in Davos, the Minister said global industry sentiment has shifted sharply—from scepticism in 2022 to active partnership interest today.

What’s next: Semicon 2.0 and deep tech awards

Looking ahead, the Minister said India aims to design and manufacture chips for 70–75% of domestic applications by 2029. Under Semicon 2.0, the focus will expand to advanced manufacturing, with a roadmap toward 3 nm and 2 nm nodes by 2035—positioning India among the world’s top semiconductor nations.

In a boost for innovators, the government will also launch Deep Tech Awards in 2026, covering semiconductors, AI, biotech, space and other frontier domains, with the first awards expected later this year.

Call to action

For chip startups, VCs, system designers and deep-tech founders, the message is clear: India’s semiconductor design ecosystem has moved from intent to execution. Early movers in fabless design, RISC-V, AI chips and power electronics now have a rare window to scale with sustained policy backing.